-- -----------------------------------------------------------------------------
--
> 4
end function
var byte port_B_low
procedure port_B_low'put( byte in x ) is
_port_B_shadow = ( _port_B_shadow & 0xF0 ) | ( x & 0x0F )
_port_B_flush
end procedure
function port_B_low'get return byte is
return portB & 0x0F
end function
var byte port_B_high
procedure port_B_high'put( byte in x ) is
_port_B_shadow = ( _port_B_shadow & 0x0F ) | ( x << 4 )
_port_B_flush
end procedure
function port_B_high'get return byte is
return portB >> 4
end function
procedure pin_A0'put( bit in x at _port_A_shadow : 0 ) is
_port_A_flush
end procedure
procedure pin_A1'put( bit in x at _port_A_shadow : 1 ) is
_port_A_flush
end procedure
procedure pin_A2'put( bit in x at _port_A_shadow : 2 ) is
_port_A_flush
end procedure
procedure pin_A3'put( bit in x at _port_A_shadow : 3 ) is
_port_A_flush
end procedure
procedure pin_A4'put( bit in x at _port_A_shadow : 4 ) is
_port_A_flush
end procedure
procedure pin_A5'put( bit in x at _port_A_shadow : 5 ) is
_port_A_flush
end procedure
procedure pin_A6'put( bit in x at _port_A_shadow : 6 ) is
_port_A_flush
end procedure
procedure pin_A7'put( bit in x at _port_A_shadow : 7 ) is
_port_A_flush
end procedure
procedure pin_B0'put( bit in x at _port_B_shadow : 0 ) is
_port_B_flush
end procedure
procedure pin_B1'put( bit in x at _port_B_shadow : 1 ) is
_port_B_flush
end procedure
procedure pin_B2'put( bit in x at _port_B_shadow : 2 ) is
_port_B_flush
end procedure
procedure pin_B3'put( bit in x at _port_B_shadow : 3 ) is
_port_B_flush
end procedure
procedure pin_B4'put( bit in x at _port_B_shadow : 4 ) is
_port_B_flush
end procedure
procedure pin_B5'put( bit in x at _port_B_shadow : 5 ) is
_port_B_flush
end procedure
procedure pin_B6'put( bit in x at _port_B_shadow : 6 ) is
_port_B_flush
end procedure
procedure pin_B7'put( bit in x at _port_B_shadow : 7 ) is
_port_B_flush
end procedure
-- ------------------------------------------------------------------
-- Fuses
-- ------------------------------------------------------------------
pragma fuse_def OSC 0x0013 {
XT = 0x0001
LP = 0x0000
INTRC_NOCLKOUT = 0x0010
INTRC_CLKOUT = 0x0011
HS = 0x0002
EXTCLK = 0x0003
ER_NOCLKOUT = 0x0012
ER_CLKOUT = 0x0013
}
pragma fuse_def WDT 0x0004 {
ON = 0x0004
OFF = 0x0000
}
pragma fuse_def WatchDog 0x0004 {
ON = 0x0004
OFF = 0x0000
}
pragma fuse_def PWRTE 0x0008 {
ON = 0x0000
OFF = 0x0008
}
pragma fuse_def PowerUp 0x0008 {
ON = 0x0000
OFF = 0x0008
}
pragma fuse_def MCLRE 0x0020 {
ON = 0x0020
OFF = 0x0000
}
pragma fuse_def LVP 0x0080 {
ON = 0x0080
OFF = 0x0000
}
pragma fuse_def CP 0x3C00 {
OFF = 0x3C00
ALL = 0x0000
_75 = 0x1400
_50 = 0x2800
}
pragma fuse_def Protection 0x3C00 {
OFF = 0x3C00
ALL = 0x0000
_75 = 0x1400
_50 = 0x2800
}
pragma fuse_def BODEN 0x0040 {
ON = 0x0040
OFF = 0x0000
}
pragma fuse_def BOR 0x0040 {
ON = 0x0040
OFF = 0x0000
}
-- ------------------------------------------------------------------
-- LKR file
-- ------------------------------------------------------------------
-- Interpretating LKR-file
const word _fuse_base = 0x2007
pragma eeprom 0x2100, 256
pragma code 4096
pragma data 0x0020-0x007F, 0x00A0-0x00EF, 0x0120-0x016F, 0x0070-0x007F
;PIC16F627A/628A PIC16F648A
;Bank0 20-7Fh 20-7Fh
;Bank1 A0h-FF A0h-FF
;Bank2 120h-14Fh, 120h-17Fh
; 170h-17Fh
;Bank3 1F0h-1FFh 1F0h-1FFh
;Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
;implemented as common RAM and mapped back to
;addresses 70h-7Fh.
;var volatile byte _shared_location_F at { 0x70,0xF0,0x170,0x1F0 }
;var volatile byte _shared_location_E at { 0x71,0xF1,0x171,0x1F1 }
;var volatile byte _shared_location_D at { 0x72,0xF2,0x172,0x1F2 }
;var volatile byte _shared_location_C at { 0x73,0xF3,0x173,0x1F3 }
;var volatile byte _shared_location_B at { 0x74,0xF4,0x174,0x1F4 }
;var volatile byte _shared_location_A at { 0x75,0xF5,0x175,0x1F5 }
;var volatile byte _shared_location_9 at { 0x76,0xF6,0x176,0x1F6 }
;var volatile byte _shared_location_8 at { 0x77,0xF7,0x177,0x1F7 }
;var volatile byte _shared_location_7 at { 0x78,0xF8,0x178,0x1F8 }
;var volatile byte _shared_location_6 at { 0x79,0xF9,0x179,0x1F9 }
;var volatile byte _shared_location_5 at { 0x7A,0xFA,0x17A,0x1FA }
;var volatile byte _shared_location_4 at { 0x7B,0xFB,0x17B,0x1FB }
;var volatile byte _shared_location_3 at { 0x7C,0xFC,0x17C,0x1FC }
;var volatile byte _shared_location_2 at { 0x7D,0xFD,0x17D,0x1FD }
var volatile byte _shared_location_1 at { 0x7E,0xFE,0x17E,0x1FE }
var volatile byte _shared_location_0 at { 0x7F,0xFF,0x17F,0x1FF }
-- some registers needed by the compiler
var volatile byte _pic_isr_w is _shared_location_0
var volatile byte _pic_add_accum is _shared_location_1
var volatile byte _ind is INDF
var volatile byte _pcl is PCL
var volatile byte _status is STATUS
var volatile byte _fsr is FSR
var volatile byte _pclath is PCLATH
const target_cpu = pic_14
pragma stack 8
pragma target chip 16F628